The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to an STI (Shallow Trench Isolation) structure and a method of fabricating the same.
Micropatterning of semiconductor devices is more and more advancing, and an STI (Shallow Trench Isolation) structure is used for element isolation. However, as the aspect ratio of the trench width to the trench depth increases, it becomes difficult to fill the trench with the conventionally used HDP (High Density Plasma Chemical Vapor Deposition)-TEOS SiO2 film. Therefore, an STI burying technique using a coating film is developed for generations in which the STI width is smaller than 100 nm.
When a coating film is used, its thickness must be increased to fill a wide STI trench.
Also, a method using a coating film of a polysilazane (to be abbreviated as PSZ hereinafter) solution is proposed.
For example, a process of curing a thick PSZ film, and planarizing the film buried in an STI trench by using CMP (Chemical Mechanical Polishing) is proposed.
If the STI width is smaller than about 70 nm, an SiN film as a mask cannot function as a stopper mask during CMP any longer. Dishing by CMP easily occurs especially in a narrow region isolated from the surrounding. This makes a good STI shape difficult to realize. In particular, it is difficult to prevent a divot and control the height of an insulating film buried in the STI trench.
FIGS. 46 to 50 illustrate the conventional fabrication method having the above problems.
As shown in a plan view of FIG. 46, active areas AA101 and AA102, an STI element isolation area STI101, and a dummy pattern DP101 are formed.
FIG. 47 is a longitudinal sectional view taken along a line A1—A1 in FIG. 46. As shown in FIG. 47, a silicon oxide film 1102 and mask silicon nitride film 1103 are formed in the surface portion of a semiconductor substrate 1101. Reactive ion etching (to be referred to as RIE hereinafter) is so performed as to leave the dummy pattern DP101 and active areas AA101 and AA102 behind, and form STI trenches in the STI element isolation area STI101.
As shown in FIG. 48, the side walls of the STI trenches are oxidized to pull back the silicon nitride film 1103.
After that, as shown in FIG. 49, a dielectric film 1106a made of PSZ is deposited on the entire surface and planarized by CMP to obtain a dielectric film 1106b. 
As shown in FIG. 50, the mask silicon nitride film 1103 and pad silicon oxide film 1102 are removed, and a sacrificial silicon oxide film (not shown) is formed. In addition, this sacrificial silicon oxide film is removed, and a gate insulating film is formed.
However, the conventional fabrication method described above has the following problems.
In the above method, to form a coating film on the bottom of an STI trench having a trench width of about 4 μm, a thick PSZ film about 600 nm thick is formed by coating. As shown in FIG. 49, the coating film is thin in a wide trench and thick in a narrow trench.
Also, as shown in FIG. 48, if each side of the mask silicon nitride film 1103 is pulled back by, e.g., about 10 nm as in the formation of the conventional STI trench, the mask width of the mask silicon nitride film 1103 decreases from about 70 nm to about 50 nm.
Consequently, when CMP is performed as shown in FIG. 49, the narrow mask silicon nitride film 1103 cannot function as the CMP stopper layer any longer in some cases.
If, however, the mask silicon nitride film 1103 is not pulled back in the step shown in FIG. 48, the silicon oxide film buried in the STI trenches recedes in the step of removing the pad silicon oxide film 1102 and sacrificial silicon oxide film. Consequently, as indicated by 1151 in FIG. 50, the side walls of the STI trenches are exposed to form a so-called divot shape.
This divot shape causes a short circuit of gate electrodes when the gate electrodes are formed in the subsequent step, and decreases the yield of the products.
In the above prior art, the STI trenches are completely filled with the PSZ coating film. However, another technique of filling STI trenches halfway and then burying a silicon oxide film in these trenches is also proposed.
That is, a PSZ film in a trench having a trench width of 1 μm or more is well converted into an SiO2 film in the subsequent BOX oxidation step. However, if the film thickness of this PSZ film is large, the film is not well converted into an SiO2 film and forms a low-density SiO2 film in a trench having a trench width of about 100 nm or less. Since the wet etching rate of the film in the trench is high, it is difficult to realize a desired STI shape by, e.g., preventing a divot and controlling the STI height.
To solve this problem, therefore, after a thin PSZ film is formed on the bottoms of STI trenches, an HDP-SiO2 film is buried in the upper portions of these STI trenches to form a hybrid structure by combining the PSZ film and HDP-SiO2 film.
FIGS. 51 to 55 are sectional views showing steps of filling STI trenches by the above method.
As shown in FIG. 51, a silicon oxide film 1301 and mask silicon nitride film 1302 are formed on the surface of a semiconductor substrate 1300, and RIE is so performed as to leave active areas behind and form STI trenches in an STI element isolation area. The side walls of these STI trenches are oxidized to form a silicon oxide film 1304.
As shown in FIG. 52, to form a dielectric film 1305 made of PSZ on the bottom of an STI trench having an STI trench width of, e.g., 1 μm or more, a thin PSZ film is formed by coating. In this step, as shown in FIG. 52, the coating film is thin in a wide trench and slightly thick in a narrow trench.
In particular, the coating film is formed up to the upper portion of the STI side wall surface facing the wide STI trench.
Then, as shown in FIG. 53, an SiO2 film 1306a is deposited by HDP so as to cover the entire surface, thereby forming a hybrid structure. As shown in FIG. 54, planarization is performed using CMP to obtain an SiO2 film 1306b. 
As shown in FIG. 55, the mask silicon oxide film 1302 is removed, and wet etching is performed to expose the surface of the active area on the semiconductor substrate 1300.
In this etching step shown in FIG. 55, the wet etching rate of the PSZ coating film exposed to the surface is about twice that of the SiO2 film 1306b, so a recess 1310 as indicated by the circle in FIG. 55 is formed.
The recess 1310 thus formed causes a short circuit of gate electrodes in the subsequent gate electrode formation step, and decreases the yield of the products.
As described above, SIT trenches are desirably filled such that a coating film does not exist on the STI side walls and exists only on the bottoms of these STI trenches regardless of whether the trench width is large or small. Unfortunately, no such fabrication method and structure can be realized by any prior art.
FIGS. 56 and 57 illustrate another process of filling STI trenches by using the conventional hybrid structure.
As shown in FIG. 56, a silicon oxide film 1402, floating gate conductive film 1403, and mask silicon nitride film 1404 are formed on the surface of a semiconductor substrate 1401, and RIE is so performed as to leave active areas behind and form STI trenches in an STI element isolation area.
Next, as shown in FIG. 57, the STI trenches are coated with a dielectric film 1412a made of PSZ. The coating film thickness is small in a wide trench and slightly large in a narrow trench.
After that, a dielectric film 1412b as shown in FIG. 57 is obtained by etching back the entire surface by wet etching.
However, in a portion indicated by a circle 1451 in FIG. 57, the conductive film 1403 may be exposed without being covered with the dielectric film 1412b. This sometimes causes a short circuit when gate electrodes are formed in the subsequent step, leading to a decrease in yield.
Still another conventional STI trench filling process is shown in FIGS. 58 and 59.
As shown in FIG. 58, a silicon oxide film 1502, floating gate conductive film 1503, and mask silicon nitride film 1504 are formed on the surface of a semiconductor substrate 1501, and RIE is so performed as to leave active areas behind and form STI trenches in an STI element isolation area.
Next, a TEOS-SiO2 film 1511 is formed on the entire surface, and the entire surface is coated with a PSZ dielectric film 1512 so that the STI trenches are completely filled.
In the step shown in FIG. 59, the dielectric film 1512 is converted into an SiO2 film 1512 by heating, the SiO2 film 1512 is planarized by CMP, and the TEOS-SiO2 film 1511 is etched by dry etching and wet etching.
In a portion indicated by a circle 1552 in FIG. 59, the surface of the conductive film 1503 is sometimes exposed without being covered with the TEOS-SiO2 film 1511 and SiO2 film 1512. This also causes a short circuit and decreases the yield.
References concerning the conventional STI trench formation methods are as follows.
Japanese Patent Laid-Open No. 2000-114362
Japanese Patent Laid-Open No. 2000-183150
Japanese Patent Laid-Open No. 2003-31650
Japanese Patent Laid-Open No. 2001-308090
Japanese Patent Laid-Open No. 2002-367980
As described above, STI trenches having different trench widths cannot be well filled by any prior art.